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19-1995; Rev 0; 4/01
Single LVDS Line Receiver in SC70
General Description
The MAX9115 is a single low-voltage differential signaling (LVDS) line receiver ideal for applications requiring high data rates, low power, and low noise. The device is guaranteed to receive data at speeds up to 200Mbps (100MHz). The MAX9115 accepts an LVDS differential input and translates it to an LVTTL/LVCMOS output. The fail-safe feature sets the output high when the inputs are undriven and open, terminated, or shorted. The device supports a wide common-mode input range, allowing a ground potential difference and common-mode noise between the driver and the receiver. The MAX9115 conforms to the ANSI TIA/EIA-644 LVDS standard. The MAX9115 operates from a single +3.3V supply, and is specified for operation from -40C to +85C. It is available in a space-saving 5-pin SC70 package. Refer to the MAX9110/MAX9112 data sheet for single/dual LVDS line drivers.
Features
o Space-Saving SC70 Package (50% Smaller than SOT23) o Guaranteed 200Mbps Data Rate o Low 350ps (max) Pulse Skew o High-Impedance LVDS Inputs When Powered Off Allow Hot Swapping o Conforms to ANSI TIA/EIA-644 LVDS Standard o Single +3.3V Supply o Fail-Safe Circuit Sets Output High for Undriven Inputs (Open, Terminated, or Shorted) o Low 150A (typ) Supply Current in Fail-Safe Mode
MAX9115
Applications
Clock Distribution Cellular Phone Base Stations Digital Cross-Connects Network Switches/Routers DSLAMs Laser Printers
MAX9115EXK-T PART
Ordering Information
TEMP. RANGE -40C to +85C PINPACKAGE 5 SC70-5 TOP MARK ACI
Typical Application Circuit
CLOCK INPUT CLOCK INPUT CLOCK INPUT
Pin Configuration
TOP VIEW
MAX9115
MAX9115
MAX9115
VCC
1 Rx
5
OUT
Rx
Rx
Rx
GND 2
IN- 3
CLOCK SOURCE Tx 100 TERMINATION
4
IN+
MAX9115
SC70
LVDS SIGNALS REFERENCE CLOCK DISTRIBUTION USING MAX9115 IN A MULTIDROP CONFIGURATION
________________________________________________________________ Maxim Integrated Products
1
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Single LVDS Line Receiver in SC70 MAX9115
ABSOLUTE MAXIMUM RATINGS
VCC to GND ...........................................................-0.3V to +4.0V IN+, IN- to GND.....................................................-0.3V to +4.0V OUT to GND ...............................................-0.3V to (VCC + 0.3V) Continuous Power Dissipation (TA = +70C) 5-Pin SC70 (derate 3.1mW/C above +70C) .............247 mW Output Short to GND (OUT) (Note 1)........................................1s Storage Temperature Range .............................-65C to +150C Maximum Junction Temperature .....................................+150C Operating Temperature Range ...........................-40C to +85C Lead Temperature (soldering, 10s) .................................+300C ESD Protection Human Body Model (IN+, IN-) .........................................6kV
Note 1: Package leads soldered to a PC board having copper ground and VCC planes. Do not exceed Maximum Junction Temperature.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, differential input voltage |VID| = 0.05V to 1.0V, input common voltage VCM = |VID/2| to 2.4V - |VID/2|, TA = -40C to +85C, unless otherwise noted. Typical values at VCC = +3.3V, TA = +25C.) (Notes 2, 3)
PARAMETER LVDS INPUTS (IN+, IN-) Differential Input High Threshold Differential Input Low Threshold Input Current Power-Off Input Current Input Resistance LVTTL/LVCMOS OUTPUT (OUT) Output High Voltage Output Low Voltage Output Short-Circuit Current SUPPLY CURRENT Supply Current ICC No load, inputs undriven (fail-safe) No load, inputs driven 150 300 7 A mA VOH VOL IOS IOH = -8.0mA Inputs open or undriven short or undriven 100 termination VID = +50mV IOL = +8.0mA, VID = -50mV VID = +50mV, VOUT = 0 VCC - 0.3 VCC - 0.3 0.25 -125 V mA V VTH VTL IIN+, IINIINO RIN1 RIN2 0.05V VID 0.6V 0.6V 2
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Single LVDS Line Receiver in SC70
AC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, CL = 15pF, differential input voltage |VID| = 0.15V to 1.0V, input common voltage VCM = |VID/2| to 2.4V - |VID /2|, input rise and fall time = 1ns (20% to 80%), input frequency = 100MHz, TA = -40C to +85C, unless otherwise noted. Typical values at VCC = +3.3V, |VID| = 0.2V, VCM = 1.2V, TA = +25C.) (Figures 2 and 3) (Notes 4 and 5)
PARAMETER Differential Propagation Delay High to Low Differential Propagation Delay Low to High Differential Pulse Skew |tPHLD - tPLHD| (Note 6) Differential Part-to-Part Skew (Note 7) Differential Part-to-Part Skew (Note 8) Rise-Time Fall-Time Maximum Operating Frequency (Note 9) SYMBOL tPHLD tPLHD tSKD1 tSKD2 tSKD3 tTLH tTHL fMAX 100 0.5 0.5 CONDITIONS MIN 1.2 1.2 TYP 1.9 1.9 MAX 3 3 350 1.3 1.8 0.8 0.8 UNITS ns ns ps ns ns ns ns MHz
MAX9115
Note 2: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production tested at TA = +25C. Note 3: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground except VTH, VTL, and VID. Note 4: AC parameters are guaranteed by design and characterization. Note 5: CL includes scope probe and test jig capacitance. Note 6: tSKD1 is the magnitude difference of differential propagation delays. tSKD1 = |tPHLD - tPLHD|. Note 7: tSKD2 is the magnitude difference of any differential propagation delays between parts operating over rated conditions at the same VCC and within 5C of each other. Note 8: tSKD3 is the magnitude difference of any differential propagation delays between parts operating over rated conditions. Note 9: fMAX pulse generator output conditions: rise-time = fall-time = 1ns (0% to 100%), 50% duty cycle, VOH = +1.3V, VOL = +1.1V. MAX9115 output criteria: 60% to 40% duty cycle, VOL = 0.25V max, VOH = 2.7V min, load = 15pF.
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Single LVDS Line Receiver in SC70 MAX9115
Typical Operating Characteristics
(VCC = +3.3V, CL = 15pF, |VID| = 0.2V, VCM = 1.2V, input rise and fall time = 1ns (20% to 80%), input frequency = 100MHz, 50% duty cycle, TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. FREQUENCY
MAX9115 toc01
SUPPLY CURRENT vs. TEMPERATURE
MAX9115 toc02
OUTPUT SHORT-CIRCUIT CURRENT vs. SUPPLY VOLTAGE
OUTPUT SHORT-CIRCUIT CURRENT (mA)
MAX9115 toc03
40
6.00
-85
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
30
-80
5.50
-75
20
5.00
-70
10
4.50
-65
0 1 10 100 1000 FREQUENCY (MHz)
4.00 -40 -15 10 35 60 85 TEMPERATURE (C)
-60 3.0 3.3 SUPPLY VOLTAGE (V) 3.6
OUTPUT HIGH VOLTAGE vs. SUPPLY VOLTAGE
MAX9115 toc04
OUTPUT LOW VOLTAGE vs. SUPPLY VOLTAGE
87.5 OUTPUT LOW VOLTAGE (mV) 87.0 86.5 86.0 85.5 85.0 84.5
MAX9115 toc05
3.60
88.0
OUTPUT HIGH VOLTAGE (V)
3.40
3.20
3.00
2.80 3.0 3.3 SUPPLY VOLTAGE (V) 3.6
84.0 3.0 3.3 SUPPLY VOLTAGE (V) 3.6
DIFFERENTIAL PROPAGATION DELAY vs. SUPPLY VOLTAGE
MAX9115 toc06
DIFFERENTIAL PROPAGATION DELAY vs. TEMPERATURE
DIFFERENTIAL PROPAGATION DELAY (ns)
MAX9115 toc07
2.2 DIFFERENTIAL PROPAGATION DELAY (ns)
2.53 2.40 2.28 2.15 tPHLD 2.03 1.90 1.86 1.73 tPLHD
2.0 tPHLD tPLHD 1.8
1.6 3.0 3.3 SUPPLY VOLTAGE (V) 3.6
-40
-15
10
35
60
85
TEMPERATURE (C)
4
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Single LVDS Line Receiver in SC70
Typical Operating Characteristics (continued)
(VCC = +3.3V, CL = 15pF, |VID| = 0.2V, VCM = 1.2V, input rise and fall time = 1ns (20% to 80%), input frequency = 100MHz, 50% duty cycle, TA = +25C, unless otherwise noted.)
DIFFERENTIAL SKEW vs. SUPPLY VOLTAGE
MAX9115 toc08
MAX9115
DIFFERENTIAL SKEW vs. TEMPERATURE
MAX9115 toc09
DIFFERENTIAL PROPAGATION DELAY vs. COMMON-MODE VOLTAGE
DIFFERENTIAL PROPAGATION DELAY (ns)
MAX9115 toc10
60 50 DIFFERENTIAL SKEW (ps) 40 30 20 10 0 3.0 3.3 SUPPLY VOLTAGE (V)
2.4 2.3 2.2 tPLHD 2.1 tPHLD 2.0 1.9 1.8
150 DIFFERENTIAL SKEW (ps)
100
50
0 3.6 -40 -15 10 35 60 85 TEMPERATURE (C)
0.1
0.6
1.1
1.6
2.1
COMMON-MODE VOLTAGE (V)
DIFFERENTIAL PROPAGATION DELAY vs. DIFFERENTIAL INPUT VOLTAGE
MAX9115 toc11
CYCLE-TO-CYCLE JITTER vs. DIFFERENTIAL INPUT VOLTAGE
57.5 CYCLE-TO-CYCLE JITTER (psp-p) 55.0 52.5 50.0 47.5 45.0 42.5
FALLING EDGE
MAX9115 toc12
2.1 DIFFERENTIAL PROPAGATION DELAY (ns)
60.0
2.0 tPHLD
RISING EDGE
1.9
tPLHD
1.8 0.1 0.2 0.3 0.4 0.5 0.6 DIFFERENTIAL INPUT VOLTAGE (V)
40.0 0.1 0.2 0.3 0.4 0.5 0.6 DIFFERENTIAL INPUT VOLTAGE (V)
TRANSITION TIME vs. LOAD CAPACITANCE
MAX9115 toc13
TRANSITION TIME vs. SUPPLY VOLTAGE
MAX9115 toc14
2.1 1.8 TRANSITION TIME (ns) tTLH 1.5 1.2 0.9 0.6 0.3 5 15 25 35 45 tTHL
580
TRANSITION TIME (ps)
tTHL 540
500 tTLH
460 55 3.0 3.3 SUPPLY VOLTAGE (V) 3.6 LOAD CAPACITANCE (pF)
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5
Single LVDS Line Receiver in SC70 MAX9115
Pin Description
VCC
PIN 1 2 3 4 5
NAME VCC GND ININ+ OUT
FUNCTION Power-Supply Input. Bypass VCC to GND with a 0.01F ceramic capacitor. Ground Inverting LVDS Differential Input Noninverting LVDS Differential Input LVTTL/LVCMOS Output
RIN1 VCC - 0.3V IN+ RIN2
Detailed Description
LVDS is intended for point-to-point communication over a controlled-impedance medium as defined by the ANSI TIA/EIA-644 and IEEE 1596.3 standards. LVDS uses a lower voltage swing than other common communication standards, achieving higher data rates with reduced power consumption while reducing EMI emissions and system susceptibility to noise. The MAX9115 is a single LVDS line receiver ideal for applications requiring high data rates, low power, and low noise. The device accepts an LVDS input and translates it to an LVTTL/LVCMOS output. The receiver detects differential signals as low as 50mV and as high as 1V within an input voltage range of 0 to +2.4V. The 250mV to 450mV differential output of an LVDS driver is nominally centered around a +1.25V offset. This offset, coupled with the receiver's 0 to +2.4V input voltage range, allows an approximate 1V shift in the signal (as seen by the receiver). This allows for a difference in ground references of the driver and the receiver, the common-mode effects of coupled noise, or both. The LVDS standards specify an input voltage range of 0 to +2.4V referenced to receiver ground.
RIN1 INGND MAX9115
OUT
Figure 1. Input Fail-Safe Network
IN+ PULSE GENERATOR *50 INRx CL MAX9115 *50 OUT
*50 REQUIRED FOR PULSE GENERATOR.
Figure 2. Propagation Delay and Transition Time Test Circuit
Fail-Safe
The fail-safe feature of the MAX9115 sets the output high and reduces supply current when: * inputs are open * inputs are undriven and shorted * inputs are undriven and terminated A fail-safe circuit is important because under these conditions, noise at the input may switch the receiver and it may appear to the system that data is being received. Open or undriven terminated input conditions can occur when a cable is disconnected or cut, or when an LVDS driver output is in high impedance. A short condition can occur because of a cable failure.
The fail-safe input network (Figure 1) samples the input common-mode voltage and compares it to VCC - 0.3V (nominal). When the input is driven to levels specified in the LVDS standards, the input common-mode voltage is less than VCC - 0.3V and the fail-safe circuit is not activated. If the inputs are open or if the inputs are undriven and shorted or undriven and parallel terminated, there is no input current. In this case, a pullup resistor in the fail-safe circuit pulls both inputs above VCC 0.3V, activating the fail-safe circuit and forcing the output high.
Applications Information
Power-Supply Bypassing
Bypass V CC with a high-frequency surface-mount ceramic 0.01F capacitor in parallel as close to the device as possible.
6
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Single LVDS Line Receiver in SC70
Differential Traces
Input trace characteristics affect the performance of the MAX9115. Use controlled-impedance PC board traces, typically 100. Match the termination resistor to this characteristic impedance. Eliminate reflections and ensure that noise couples as common mode by running the differential traces close together. Reduce skew by matching the electrical length of the traces. Excessive skew can result in a degradation of magnetic field cancellation. Input differential signals should be routed close to each other to cancel their external magnetic field. Maintain a constant distance between the differential traces to avoid discontinuities in differential impedance. Minimize the number of vias to further prevent impedance discontinuities.
VINVID = 0 VIN+ tPLHD tPHLD VID VID = 0
MAX9115
80% VOUT 50% 20% tTLH COMMON-MODE VOLTAGE: VCM = (VIN+ + VIN-) / 2 DIFFERENTIAL INPUT VOLTAGE: VID = (VIN+) - (VIN-)
80% 50% 20% tTHL
VOH
VOL
Figure 3. Propagation Delay and Transition-Time Waveforms
Cables and Connectors
Transmission media should typically have a controlled differential impedance of 100. Use cables and connectors that have matched differential impedance to minimize impedance discontinuities. Avoid the use of unbalanced cables such as ribbon or simple coaxial cable. Balanced cables such as twisted pair offer superior signal quality and tend to generate less EMI due to canceling effects. Balanced cables tend to pick up noise as common mode, which is rejected by the LVDS receiver.
(LVTTL/LVCMOS OUTPUT)
C1 0.01F VCC
U1 OUT
GND
Termination
The MAX9115 requires an external termination resistor. The termination resistor should match the differential impedance of the transmission line. Termination resistance is typically 100 but may range between 90 to 132, depending on the characteristic impedance of the transmission medium. When using the MAX9115, minimize the distance between the input termination resistor and the MAX9115 receiver inputs. Use 1% surface-mount resistors.
IN-
IN+
R1
Board Layout
For LVDS applications, a four-layer PC board that provides separate layers, power, ground, and input/output signals is recommended. Keep the LVDS input signals away from the output LVCMOS/LVTTL signal to prevent coupling (Figure 4). To minimize crosstalk, do not run the output in parallel with the inputs. Extend the ground pin trace under the package to the other side between IN+ and OUT to provide isolation between IN+ and OUT.
U1: MAX9115 R1, C1 ARE 0402 TYPE
(LVDS INPUTS)
Figure 4. Board Layout
Chip Information
TRANSISTOR COUNT: 201 PROCESS: CMOS
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Single LVDS Line Receiver in SC70 MAX9115
Package Information
SC70, 5L.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
8 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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